View STAR-1000_5528990.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 1 of 24 STAR-1000 1 m pixel radiation - hard cmos image sensor datasheets
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 2 of 24 table of contents 1. sensor description ............................................................................................................. .................. 4 1.1. the pixel array................................................................................................................ ........................ 5 1.2. addressing logic............................................................................................................... ...................... 5 1.3. the column amplifiers .......................................................................................................... ................. 6 1.4. the output amplifier and analog multiplexer ................ .................................................................... .... 6 1.5. the adc ........................................................................................................................ ........................ 6 2. image sensor specifications .................................................................................................... ....... 7 2.1. general specifications ......................................................................................................... ................... 7 2.2. electro-optical specifications................................................................................................. ................ 7 2.3. spectral response curve..... ................................................................................................... .................. 9 2.4. photo-voltaic response ......................................................................................................... .................. 9 2.5. absolute maximum ratings ....................................................................................................... ........... 10 2.6. dc operating conditions ........................................................................................................ .............. 10 3. timing and control signals ..................................................................................................... .... 11 3.1. row selection and reset timing ............................... .................................................................. ........... 11 3.2. pixel read-out timing.......................................................................................................... .................. 13 4. pin list ....................................................................................................................... ................................. 14 5. packaging and geometrical constraints ........................................................................... 19 5.1. package drawing................................................................................................................ ................... 19 5.2. die alignment .................................................................................................................. ..................... 20 6. ordering information........................................................................................................... ........... 21 appendix a: STAR-1000 evaluation system ............................................................................... 22 appendix b: frequently asked questions ............................................................................... 23
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 3 of 24 document history record issue date description of changes 6.1 4 th april, 2003 p6: table 1: image sensor specs updated. p8: spectral response curve and photovoltaic response curve added. p18: package drawing added. p19: appendix a added. p20: appendix b added. 6.2 23 rd april, 2003 p6: table 1: image sensor specs updated. p8: photovoltaic response curve updated. p17: table 9: vdd_ana connected internally? 6.3 8 th july, 2003 p6: table 2: values updated. p9: table 3 and 4 added. p13: pin connection drawing added. p14: table 7 updated. p16: notes added. p17: package drawing updated. p18: die alignment added. 6.4 27 th september 2004 p1: layout changed. p7: table 2 updated. p10: table 3 updated. p12: table 5: f: r changed into ld_y p17: table 7: pin 58. description added. p20: figure 5 updated. 6.5 4 th january 2005 added equivalent cypress part numbers and cypress logo. added cypress document # 38-05714 rev ** in the document footer.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 4 of 24 1. sensor description the STAR-1000 is a cmos image sensor with 1024 by 1024 pixels on a 15- m pitch. it features on-chip fixed pattern noise (fpn) correction, a programmable gain amplifier and a 10-bit analog to digital converter (adc). all circuits are designed using the radiation tolerant design rules for cmos image sensors to allow a high tolerance against total dose effects. registers that can be directly accessed by the external controller contain the x- and y-addresses of the pixels to be read. this architecture provides flexible operation and allows different operation modes like (multiple) windowing, sub sampling, etc. the image sensor contains five sections: the pixel array, the x-and y addressing logic, the column amplifiers, the output amplifier and the adc. figure 1 shows an outline diagram of the sensor, including an indication of the main control signals. the following paragraphs explain in more detail the function and operation of the different imager parts. part numbers color or b/w STAR-1000 cyiism1000aa-hfc -(preliminary) b&w fi g ure 1: ima g e sensor outline dia g ram pixel array 1024 x 1024 pixels y address decoder and logic rese t reset ds vre f 10 a0 ? a9 column amplifiers s r x re g ister 1024 1024 1024 clk x 1024 x address decoder 10 10 buffe r 1024 latch latch progr. gain amplifier multiplexer bl ac kr ef cal g0f g1 ain1 ain2 ain 3 sel0 sel1 aout 10-bit adc 10 d0 ? d9 clk adc ain 1024 rst rd col ld y ld x rst rd 1024 rst sig
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 5 of 24 1.1. the pixel array the pixel array contains 1024 by 1024 active pixels at 15 m pitch. each pixel contains one photo diode and three transistors (figure 2). the photo diode is always in reverse bias. at the beginning of the integration cycle a pulse is applied to the reset line (gate of t1) bringing the cathode of d1 to the reset voltage level. during the integration period photon-generated electrons accumulate on the diode capacitance, reducing the voltage on the gate of t2. the real illumination-dependent signal is the different between the reset level and the output level after integration. this difference is made in the column amplifiers. t2 acts as a source follower and t3 allows connection of the pixel signal (reset level and output level) to the vertical output bus. the reset-lines and the read-lines of the pixe ls in a row are connected together to the y-decoder logic; the outputs of the pixels in a column are connected together to a column amplifier. 1.2. addressing logic the addressing logic allows direct addressi ng of rows and columns. instead of the one-hot shift registers that are often used, address decoders are implemented. one can select a line by presenting the required address to the address input of the device and latching it to the y-decoder logic. presenting the x-address to the device address input and latching it to the x-address decoder can select a column. a typical line read out sequence will first select a line by applying the y-address to the y-decoder. activation of the ?ld_y? input on the y-logic will connect the pixel outputs of the selected line to the column amplifiers. the individual column amplifier outputs can be connected to the output amplifier by applying the respective x- addresses to the x address decoder. applying the appropriate y-address to the y- decoder and activating the ?reset? input reset a line. the integration time of a row is the time between the last reset of this row and time when it is selected for read-out. reset read column bus t1 t2 t3 fi g ure 2: active p ixel electrical dia g ram
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 6 of 24 the y-decoder logic has two different reset inputs: ?reset? and ?reset_ds?. activation of ?reset? will reset the pixel to the vdd level; activation of ?reset_ds? will reset the pixel to the voltage level on the ?vref? input. this feature allows the application of the so-called dual slope integration (see appendix b). if dual slope integration is not needed ?vref? can be tied to vdd and ?reset_ds? must never be activated. 1.3. the column amplifiers all outputs from the pixels in a column are connected in parallel to a column amplifier. this amplifier samples the output voltage and the reset level of the pixel whose row is selected at that moment and presents these voltage levels to the output amplifier. as a result the pixels are always reset immediately after read-out as part of the sample procedure and the maximum integration time of a pixel is the time between two read cycles. 1.4. the output amplifi er and analog multiplexer the output amplifier combines subtraction of pixel signal level from reset level with a programmable gain amplifier. since the amplifier is ac coupled it also contains a provision to maintain and restore the proper dc level. an analogue signal multiplexer feeds the pixel signal to the final unity gain buffer to provide the required drive capability. apart from the pixel signal also three other external analogue signals can be fed to the output buffer. all these signals can be digitalised by the on-chip adc if the output of this buffer is externally connected to the input of the adc. the purpose of the additional analogue inputs (?a_in1?, ?a_in2? and ?a_in3?) is to allow a possibility to process other analogue signals through the image sensors signal path. these signals can thus be converted by the adc and processed by the image controller fpga. the additional analogue inputs are intended for low frequency or dc signals and have a reduced bandwidth, compared with the image signal path. 1.5. the adc the image sensor has a 10-bit adc that is electrically separated from the rest of the image sensor circuits and can be powered down if an external adc is used. the conversion takes place at the falling edge of the clock and the output pins can be disabled to allow operation of the device in a bus structure.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 7 of 24 2. image sensor specifications 2.1. general specifications table 1: general specification of the STAR-1000 sensor parameter specification comment detector technology cmos active pixel sensor pixel structure 3-transistor active pixel radiation-tolerant pixel design. photodiode high fill factor photodiode using n-well technique sensitive area format 1024 x 1024 pixels pixel size 15 x15 m 2 pixel output rate 12 mhz speed can be exchanged for power consumption windowing x- and y- addressing random programmable electronic shutter electronic rolling shutter. range: 1 : 1024 integration time is variable in time steps equal to the row readout time. total dose radiation tolerance > 230krad (si) pixel test structures with a similar design have shown total dose tolerance up to several mrad. radiation tests on similar image sensor were performed up to 230 krad. expected equivalent fluence at 10 mev 3.10 10 proton/cm 2 tbd. sel threshold > 28 mev cm 3 mg -1 a similar design was tested up to 28 mev without any latch up noticeable. no other evaluations have been done yet. 2.2. electro-optical specifications table 2: electro-optical specifications of the STAR-1000 sensor value comment parameter typical value unit spectral range 400 - 1000 nm quantum efficiency x fill factor 20% average over the visual range. see spectral response curve. full well capacity 135.000 e-
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 8 of 24 value comment parameter typical value unit saturation capacity to meet non-linearity within + 5% 99.000 e- output signal swing 1.1 v conversion gain 11.4 v/e- ktc noise 35 e- dynamic range 72 db fixed pattern noise local: 1 < 0.30% global: 1 <0.56% of full well photo response non- uniformity at qsat/2 (rms) local: 1 < 0.67% global: <3.93% of full well average dark current at 293 k 223 pa/cm 2 dark current signal 3135 e- / s dsnu signal 1.055 % of vsat optical cross-talk at 600 nm vertical: 16 % horizontal: 17.5 % anti-blooming capacity x 1000 output amplifier gain x1, x2.47, x4.59 and x8.64 controlled by 2 bits analogue input bandwidth 9.5 mhz analogue input signal range 0.1 to 4.9 v analog-digital converter 10 bit radiation-tolerant version of the adc on ibis4 and other image sensors. adc differential non- linearity (dnl) <= 3.5 lsb adc integral non- linearity (inl) <= 5.8 lsb integral non-linearity of adc is better than linearity of image sensor. supply voltage 5 v digital input signals are 3.3 v compatible power dissipation < 350 < 100 mw with internal adc powered. without internal adc powered. both values measured at nominal speed (12 mhz).
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 9 of 24 2.3. spectral response curve 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 400 500 600 700 800 900 1000 w avelenght [nm ] spectral response [a/w] qe 0.01 qe qe 0.1 qe 0.2 qe 0.3 2.4. photo-voltaic response 0 0.2 0.4 0.6 0.8 1 1.2 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 number of electrons voltage swing at output [v]
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 10 of 24 2.5. absolute maximum ratings table 3:absolute maximum ratings characteristics symbol limits units remarks min max any supply voltage -0.5 +7 v voltage on any input terminal -0.5 vdd + 0.5 v operating temperature 0 +60 c temperature range to be confirmed by evaluation testing storage temperature -10 +60 c not longer than 1 hour. temperature range to be confirmed by evaluation testing soldering temperature na 260 (tbc) c maximum solder temperature to be confirmed by evaluation testing 2.6. dc operating conditions table 4: dc operating conditions symbol parameter limits units min typ max vdda analog supply of the image core. 5 v vddd digital supply of the image core. 5 v vdd_adc_ana analog supply of the adc circuitry. 5 v vdd_adc_dig digital supply of the adc circuitry. 5 v vdd_dig_out power supply of adc digital output stage. 5 v vres reset level for reset signal. 5 v vref reset level for reset_ds signal. 4 5 v gnda analog ground of the image core. 0 v gndd digital ground of the image core. 0 v gnd_adc_ana analog ground of the adc circuitry. 0 v gnd_adc_dig digital ground of the adc circuitry. 0 v v ih logical ?1? input voltage. 1.8 vddd v v il logical ?0? input voltage. 0 1 v v oh logical ?1? output voltage. 4.25 vddd v v ol logical ?0? output voltage. 1 v
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 11 of 24 3. timing and control signals the pixels addressing is done by direct addressing of rows and columns. this approach has the advantage of full flexibility when accessing the pixel array: multiple windowing and sub-sampled read-out are possible by proper programming. the following paragraphs clarify the timing for row- and column readout. 3.1. row selection and reset timing figure 3 shows the timing of the line sequence control signals. the timing constraints are given in table 5. the address, presented at the address io pins (a0?a9) is latched in with the ld-y pulse (active low). after latching; the ex ternal controller can already produce a new address. latching in a y-address selects the addres sed row and connects the pixel outputs of that row to the column amplifiers. through the sequence of the s and r pulse and the reset pulse in-between the pixel output signal and reset level are sampled and produced at the output of the column amplifier (to do the fpn double sampling correction). at this time horizontal read-out of the selected row can start and another row can be reset to effectuate reduced integration time (electronic rolling shutter). table 5 shows the timing constraints for the horizontal or line-select timing. figure 3: line selection and reset sequence a0 ? a9 ld y \ row selected for readout internal s rese t r b d e b a c row selected for reset reset address d f g k l m kl m i h cal (once eac h frame) time available for readout of row y-1 idle time available for x-readout of row y row readou t read address
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 12 of 24 table 5: timing constraints of line sequence symbol min. typ. description a 3.6 s delay between selection of a new row and falling edge on s. minimal value: for maximum speed a new row can already be selected during x-readout of the previous row. b 0.4 s duration of s and r pulse. c 0 100 ns delay between falling edge of s and rising edge of reset. d 200 ns minimum duration of reset pulse. e 1.6 s delay between falling edge of reset and falling edge of r. f 0 100 ns minimum delay between falling edge on ld_y and rising edge of reset. g 100 ns minimum required extension of y-address after falling edge of reset pulse. h 100 ns 200 ns position of cal pulse after rising edge of s. the cal pulse must only be given once per frame. i 100 ns 1 s duration of cal pulse. k 10 ns address set-up time. l 20 ns load register value. m 10 ns address stable after load.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 13 of 24 3.2. pixel read-out timing figure 4 shows the timing of the pixel readout sequence. the external digital controller presents a column address that is latched in by the rising edge of the ld_x pulse. after decoding the x-address the column selection is clocked in the x-register by clk-x. the output amplifier uses the same pulse to subtract the pixel output level from the pixel-reset level and the signal level. this causes a pipeline effect such that the analog output of the first pixel is effectively present at the device output terminal at the third rising edge of the x-clk signal. the adc conversion starts at the falling edge of the clk-adc signal and produces a valid digital output 20ns after this edge. the timing of these signals is given in table 3. table 6: timing constraints of column read out symbol min typ description a 40 ns address setup time b 40 ns address valid time c 0 20 ns adc output valid after falling edge of clk_adc a0 ? a9 x1 a row idle time x2 x3 x4 x5 x6 x7 ld x clk x b analog output x8 x1 x2 x3 x4 x5 x6 undefined output level clk adc x1 x2 x3 x4 d9 ? d0 c fi g ure 4: column selection and read-out se q uence
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 14 of 24 4. pin list table 6 is a list of the pin connections; the following tables group the connections by their functionality. figure 3: STAR-1000 pin connections
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 15 of 24 table 7: pin list of the STAR-1000 sensor pin pin name pin type pin description 1 a3 input 2 a4 input 3 a5 input 4 a6 input 5 a7 input 6 a8 input 7 a9 input digital input. address inputs for row and column addressing. a9=lsb, a0=msb. 8 ld_y input digital input. latch address (a0?a9) to y-register (0 = track, 1 = hold). 9 ld_x input digital input. latch address (a0?a9) to x-register (0 = track, 1 = hold). 10 vdda supply analog power supply of the imager (typical 5v). 11 gndd ground digital ground of the imager. 12 gnda ground analog ground of the imager. 13 clk_x input digital input. clock x-register (output valid & stable when clk_x is high). 14 reset_ds input digital input (high active). resets row indicated by y- address (see sensor timing diagram). reset_ds can be used for dual-slope integration (see faq). connect to gnd for normal operation. 15 vddd supply digital supply of the image sensor. 16 reset input digital input (high active). resets row indicated by y- address (see sensor timing diagram). 17 s input digital input (high active). control signal for column amplifier (see sensor timing diagram). 18 r input digital input (high active). control signal for column amplifier (see sensor timing diagram). 19 nbias_dec input analog input. biasing of address decoder. connect with 100k ? to vdda and decouple with 100 nf to gnd. 20 a_in2 input 21 a_in3 input 22 a_in1 input additional analog inputs. for proper conversion with on-chip adc the input signal must lie within the output signal range of the image sensor (approximately +2v to +4v). 23 a_sel1 input 24 a_sel0 input selection of analog channel: ?00? selects image sensor (?01? selects a_in1; ?10? a_in2 and ?11? a_in3). 25 nbias_oamp input analog input. bias of output amplifier (speed/power control). connect with 100k ? to vdda and decouple with 100 nf to gnd for 12.5 mhz output rate (lower resistor values yield higher maximal pixel rates at the cost of extra power dissipation). 26 pbias input analog input. biasing of the multiplexer circuitry. connect with 20k ? to gnd and decouple with 100nf to vdd. 27 g1 input di g ital in p ut. select out p ut am p lifier g ain value: g0 =
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 16 of 24 pin pin name pin type pin description 28 g0 input lsb; g1 = msb (?00? = unity gain; ?01? = x2; ?10?= x4; ?11?=x8). 29 cal input digital input (active high). initialization of output amplifier. output amplifier will output blackref in unity gain mode when cal is high (1). apply pulse pattern (see sensor timing diagram). 30 out output analog output video signal. to be connected to the analog input of the internal (pin 52) 10-bit adc or an external adc. 31 blackref input analog input. control voltage for output signal offset level. buffered on-chip, the reference level can be generated by a 100k ? resistive divider. connect to 2 v dc for use with on-chip adc. 32 vdda supply analog power supply of image core (typical 5 v). 33 vddd supply digital power supply of image core (typical 5v). 34 gnda ground analog ground of image core. 35 gndd ground digital ground of image core. 36 nbias_array input analog input. biasing of the pixel array. connect with 1m ? to vdda and dec ouple with 100 nf capacitor to gnd. 37 testpix_out output output of single test pixel. can be used for electro- optical evaluation. 38 testpix_reset input digital input (active high). reset signal of single test pixel. used to reset the single test pixel during electro- optical evaluation. 39 n.c. 40 n.c. 41 n.c. 42 n.c. 43 n.c. 44 n.c. 45 n.c. 46 n.c. 47 n.c. 48 testpixarray output analog output of an array of 20 x 35 test pixels where all photodiodes are connected in parallel. can be used for electro-optical evaluation. 49 photodiode output plain photo diode (without circuitry). area of the photodiode = 20 x 35 pixels. can be used for electro- optical evaluation. 50 nbias_ana input 51 nbias_ana2 input analog input. analog biasing of the adc circuitry. connect with 100k ? to vdda and decouple with 100nf to gnd. 52 in_adc input analog input of the internal adc. connect to analog output of image sensor (pin 30). input range (typically 2v and 4v) of the internal adc is set between by vlow_adc (pin 55) and vhigh_adc (pin 62). 53 vdd_adc_ana supply analog power supply of the adc (typical 5v). 54 gnd_adc_ana ground analog ground of the adc.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 17 of 24 pin pin name pin type pin description 55 vlow_adc input low reference voltage of internal adc. nominal input range of the adc is between 2v and 4v. the resistance between vlow_adc and vhigh_adc is about 1.5 k ? . connect with 1k5 ? to gnd and decouple with 100nf to gnd. 56 n.c. 57 pbiasdig2 input connect with 20k to gnd and decouple with 100nf to vdda. 58 bitinvert input digital input. inversion of the adc output bits. 0 = invert output bits (0 => black: 1023; white: 0), 1 = no inversion of output bits (black: 0; white: 1023). 59 tri_adc input digital input. tri-state control of digital adc outputs (1 = tri-state; 0 = normal mode). 60 d0 input adc output bits. d0 = lsb, d9=msb. 61 clk input digital input. adc clock. adc converts on falling edge. 62 vhigh_adc input high reference voltage of internal adc. nominal input range of the adc is between 2v and 4v. the resistance between vlow_adc and vhigh_adc is about 1.5 k ? . connect with 1k1 ? to vdda and decouple with 100nf to gnd. 63 gnd_adc_ana ground analog ground of the adc circuitry. 64 vdd_adc_ana supply analog supply of the adc circuitry (typical 5v). 65 vdd_adc_dig supply digital supply of the adc circuitry (typical 5v). 66 gnd_adc_dig output digital ground of the adc circuitry. 67 vdd_dig_out supply power supply of adc digital output. connect to 5v for or normal operation. can be brought to lower voltage when image sensor must be interfaced to low voltage periphery. 68 d1 output 69 d2 output 70 d3 output 71 d4 output 72 d5 output adc output bits. d0 = lsb, d9=msb. 73 vdda supply analog supply of the image core (typical 5v). 74 gnda ground analog ground of the image core (typical 5v). 75 gnd_ab supply anti-blooming drain control voltage. default: connect to ground, the anti-blooming is operational but not maximal. apply 1 v dc for improved anti-blooming. 76 vref supply analog supply. reset level for reset_ds. can be used for extended optical dynamic range. see faq for more details. 77 vres supply analog supply. reset level for reset (typical 5v). 78 d6 output 79 d7 output 80 d8 output 81 d9 output adc output bits. d0 = lsb, d9=msb.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 18 of 24 pin pin name pin type pin description 82 a0 input 83 a1 input 84 a2 input digital input. address inputs for row and column addressing. a9=lsb, a0=msb. notes : 1. all pins with the same name can be connected together. 2. unused inputs must always be tied to an appropriate level, e.g. vdd or gnd. 3. note on power up behaviour: at power-on, the image sensor is in an undefined state. it is advised that after start-up an address is latched asap into the y-decoder and the x-decoder to prevent high current consumption. 4. there?s no on-chip power supply reject ion whatsoever. this means that every noise signal on the analog supply voltages is copied directly to the analog video signal (decoupling of the supply voltages as close as possible to the image sensor is recommended).
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 19 of 24 5. packaging and geometrical constraints 5.1. package drawing the detector is packaged in an 84-pin j-leaded package. the detector is mounted into position with thermally and electrically conductive adhesive. the bottom plate of the cavity will be electrically connected to a ground pin. the detector will be positioned into the cavity such that the optical centre of the detector coincides with the geometrical centre of the cavity within a tolerance of 50 m in x- and y direction. the toleran ce on the parallelism of the detector is 50 m in x- and y-direction. figure 4: package drawing
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 20 of 24 5.2. die alignment pin 1 parallelism in x and y within 50 m glass window: 1.0 +/- 0.05 window adhesive: 0.08 0.02 die: 0.508 0.01 die adhesive 0.08 0.02 section a -a a a bonding cavity 0.508 0.051 die cavity: 0.508 0.051 drawing not to scale center of silicium center of cavity and of fpa offset between center of silicium and center of cavity: x = - 52 m y = - 200 m x y 200 u 52 u figure 5: die alignment
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 21 of 24 6. ordering information fillfactory part number cypress semiconductor part number STAR-1000 cyis1sm1000aa-hfc - (preliminary) disclaimer fillfactory image sensors are only warranted to meet the specifications as described in the production data sheet. fillfactory reserves the right to change any information contained herein without notice. please contact info@fillfactory.com for more information.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 22 of 24 appendix a: STAR-1000 evaluation system for evaluating purposes an STAR-1000 evaluation kit is available. the STAR-1000 evaluation kit consists of a multifunctional digital board (memory, sequencer and ieee 1394 fire wire interface ) and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images from the sensor. all acquired images can be stored in different file formats (8 or 16-bit). all setting can be adjusted on the fly to evaluate the sensors specs. default register values can be loaded to start the software in a desired state. please contact fillfactory ( info@fillfactory.com ) if you want any more information on the evaluation kit.
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 23 of 24 appendix b: frequently asked questions q: how does the dual slope extended dynamic range mode works? a: dual slope is a method to extend the dynamic range of a normally linear- transfer imager, by combining the images taken with a long integration time (dark areas of a scene) and a short integr ation time (bright areas of a scene) into one image and this in one integration time cycle i.e. without combining two different images. the resulting electro- optical transfer curve is bi-linear. please look at our website to find some pictures with extended dynamic range: http://www.fillfactory.be/htm/technology/htm/dual-slope.htm .
STAR-1000 datasheet cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 contact: info@fillfactory.com document #:38-05714 rev.**(revision 6.5) page 24 of 24 document history page document title: STAR-1000 1m pixel radiation hard cmos image sensor document number: 38-05714 rev. ecn no. issue date orig. of change description of change ** 310213 see ecn sil initial cypress release eod

▲Up To Search▲

Price & Availability of STAR-1000

	To Download STAR-1000 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .